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ADE7753
Interrupt Timing
The ADE7753 Serial Interface section should be reviewed first
before reviewing the interrupt timing. As previously described,
when the IRQ output goes low, the MCU ISR must read the
interrupt status register to determine the source o f th e interrupt.
When reading the status register contents, the IRQ output is set
high on the last falling edge of SCLK of the first byte transfer
(read interrupt status register command). The IRQ output is
held high until the last bit of the next 15-bit transfer is shifted
out (interrupt status register contents)—see Figure 45 . If an
interrupt is pending at this time, the IRQ output goes low again.
If no interrupt is pending, the IRQ output stays high.
TEMPERATURE MEASUREMENT
The ADE7753 also includes an on-chip temperature sensor. A
temperature measurement can be made by setting Bit 5 in the
mode register. When Bit 5 is set logic high in the mode register,
the ADE7753 initiates a temperature measurement on the next
zero crossing. When the zero crossing on Channel 2 is detected,
the voltage output from the temperature sensing circuit is
connected to ADC1 (Channel 1) for digitizing. The resulting
code is processed and placed in the temperature register
(TEMP[7:0]) approximately 26 μs later (96/CLKIN seconds). If
enabled in the interrupt enable register (Bit 5), the IRQ output
goes active low when the temperature conversion is finished.
The contents of the temperature register are signed (twos
complement) with a resolution of approximately 1.5 LSB/°C.
The temperature register produces a code of 0x00 when the
ambient temperature is approximately ?25°C. The temperature
measurement is uncalibrated in the ADE7753 and has an offset
tolerance as high as ±25°C.
ADE7753 ANALOG-TO-DIGITAL CONVERSION
The analog-to-digital conversion in the ADE7753 is carried out
using two second-order Σ-Δ ADCs. For simplicity, the block
A Σ-Δ modulator converts the input signal into a continuous
serial stream of 1s and 0s at a rate determined by the sampling
clock. In the ADE7753, the sampling clock is equal to CLKIN/4.
The 1-bit DAC in the feedback loop is driven by the serial data
stream. The DAC output is subtracted from the input signal. If
the loop gain is high enough, the average value of the DAC out-
put (and therefore the bit stream) can approach that of the input
signal level. For any given input value in a single sampling interval,
the data from the 1-bit ADC is virtually meaningless. Only when
a large number of samples are averaged is a meaningful result
obtained. This averaging is carried out in the second part of the
ADC, the digital low-pass filter. By averaging a large number of
bits from the modulator, the low-pass filter can produce 24-bit
data-words that are proportional to the input signal level.
The Σ-Δ converter uses two techniques to achieve high resolution
from what is essentially a 1-bit conversion technique. The first
is oversampling. Oversampling means that the signal is sampled
at a rate (frequency), which is many times higher than the
bandwidth of interest. For example, the sampling rate in the
ADE7753 is CLKIN/4 (894 kHz) and the band of interest is
40 Hz to 2 kHz. Oversampling has the effect of spreading the
quantization noise (noise due to sampling) over a wider
bandwidth. With the noise spread more thinly over a wider
bandwidth, the quantization noise in the band of interest is
lowered—see Figure 48. However, oversampling alone is not
efficient enough to improve the signal-to-noise ratio (SNR) in
the band of interest. For example, an oversampling ratio of 4 is
required just to increase the SNR by only 6 dB (1 bit). To keep
the oversampling ratio at a reasonable level, it is possible to
shape the quantization noise so that the majority of the noise
lies at the higher frequencies. In the Σ-Δ modulator, the noise is
shaped by the integrator, which has a high-pass-type response
for the quantization noise. The result is that most of the noise is
at the higher frequencies where it can be removed by the digital
diagram in Figure 47 shows a first-order Σ-Δ ADC. The converter
is made up of the Σ-Δ modulator and the digital low-pass filter.
MCLK/4
SIGNAL
DIGITAL
FILTER
ANTILALIAS
FILTER (RC)
SHAPED
SAMPLING
FREQUENCY
ANALOG
LOW-PASS FILTER
R
C
+
–
INTEGRATOR
+
–
LATCHED
COMPARATOR
DIGITAL
LOW-PASS
FILTER
24
NOISE
NOISE
V REF
0
2
447
894
FREQUENCY (kHz)
.....10100101.....
HIGH RESOLUTION
1-BIT DAC
SIGNAL
OUTPUT FROM DIGITAL
LPF
02875-0-046
Figure 47. First-Order Σ -? ADC
NOISE
0
2
447
FREQUENCY (kHz)
894
02875-0-047
Figure 48. Noise Reduction Due to Oversampling and
Noise Shaping in the Analog Modulator
Rev. C | Page 22 of 60
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